HD64F2145 Datasheet, PDF (663/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Reset state
STBY pin = High
RES pin = Low
RES pin = High
Program execution state
High-speed mode
(main clock)
SLEEP instruction
Any interrupt
Program halt state
STBY pin = Low
Hardware
standby mode
SSBY = 0, LSON = 0
Sleep mode
(main clock)
SCK2 to
SCK0 are
0
SCK2 to
SCK0 are
not 0
Medium-speed
mode
(main clock)
SLEEP
instruction
External
interrupt *³
SLEEP
instruction
SLEEP instruction
SSBY = 1, PSS = 1,
DTON = 1, LSON = 0
After the oscillation
stabilization time
(STS2 to STS0), clock
switching exception
handling
SLEEP instruction
SSBY = 1, PSS = 1,
DTON = 1, LSON = 1
Clock switching
exception handling
Subactive mode
(subclock)
Interrupt *¹
LSON bit = 0
SLEEP
instruction
Interrupt *¹
LSON bit = 1
SLEEP instruction
Interrupt *²
SSBY = 1,
PSS = 0, LSON = 0
Software
standby mode
SSBY = 1,
PSS = 1, DTON = 0
Watch mode
(subclock)
SSBY = 0,
PSS = 1, LSON = 1
Subsleep mode
(subclock)
: Transition after exception processing
: Power-down mode
Notes: 1. NMI, IRQ0 to IRQ2, IRQ6, IRQ7, and WDT1 interrupts
2. NMI, IRQ0 to IRQ7, WDT0, WDT1, TMR0, and TMR1 interrupts
3. NMI, IRQ0 to IRQ2, IRQ6, and IRQ7 interrupts
• When a transition is made between modes by means of an interrupt, the transition cannot be made
on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the
interrupt request.
• Always select high-speed mode before making a transition to watch mode or sub-active mode.
Figure 26.1 Mode Transition Diagram
Rev. 2.0, 08/02, page 623 of 788