HD64F2145 Datasheet, PDF (659/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit Bit Name Initial Value R/W
2 SCK2 0
R/W
1 SCK1 0
R/W
0 SCK0 0
R/W
Legend
X: Don't care
Description
System Clock Select 2 to 0
Selects a clock for the bus master in high-speed mode or
medium-speed mode.
When making a transition to subactive mode or watch
mode, SCK2 to SCK0 must be cleared to 0.
000: High-speed mode
001: Medium-speed clock: ø/2
010: Medium-speed clock: ø/4
011: Medium-speed clock: ø/8
100: Medium-speed clock: ø/16
101: Medium-speed clock: ø/32
11X: —
Table 26.1 Operating Frequency and Wait Time
STS2 STS1 STS0 Wait Time 20 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz Unit
0 0 0 8192 states 0.4
0.8
1.0
1.3
20.
4.1
ms
0 0 1 16384 states 0.8
1.6
2.0
2.7
4.1
8.2
0 1 0 32768 states 2.0
3.3
4.1
5.5
8.2
16.4
0 1 1 65536 states 4.1
6.6
8.2
10.9 16.4 32.8
1 0 0 131072 states 8.2
13.1 16.4 21.8 32.8 65.5
1 0 1 262144 states 16.4 26.2 32.8 43.6 65.6 131.2
1 1 0 Reserved







1 1 1 16 states* 0.8
1.6
2.0
2.7
4.0
8.0
µs
Shaded cells indicate the recommended specification.
Note:* This setting cannot be made in the flash-memory version of this LSI.
Rev. 2.0, 08/02, page 619 of 788