HD64F2145 Datasheet, PDF (483/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Start condition issuance
SCL
(master output)
1 23 4 56 789 1 23 4
SDA
(master output)
SDA
(slave output)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Slave address
R/
Bit 7 Bit 6 Bit 5 Bit 4
[6]
Data 1
A
IRIC
ICDRF
ICDRS
ICDRR
Address+R/
Data 1
[7]
Address+R/
User processing
[8] IRIC clear
[10] ICDR read
Figure 16.22 Example of Slave Receive Mode Operation Timing (1)
(MLS = ACKB = 0)
SCL
(master output) 8
SDA
(master output) ^{Bit 0}
Data n-2
SDA
(slave output)
91 234 5 6 789
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[11]
Data n-1
[11]
A
A
IRIC
Start condition detection
1 2345 6789
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data n
[11]
[11]
A
ICDRF
ICDRS Data n-2
ICDRR
User processing
Data n-2
[9] Wait for one frame
[13] IRIC clear
Data n-1
Data n-1
[13] IRIC clear _{[10] ICDR read}
[10] ICDR read
(Data n-2)
(Data n-1)
[9] Set ACKB = 1
Data n
Data n
[13] IRIC clear
[14] ICDR read
(Data n)
[15] IRIC clear
Figure 16.23 Example of Slave Receive Mode Operation Timing (2)
(MLS = ACKB = 0)
Rev. 2.0, 08/02, page 443 of 788