HD64F2145 Datasheet, PDF (349/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

13.4 Operation
13.4.1 PWM Decoding (PDC Signal Generation)
The timer connection facility and TMR_X can be used to decode a PWM signal in which 0 and 1
are represented by the pulse width. To do this, a signal in which a rising edge is generated at
regular intervals must be selected as the IHI signal.
The timer counter (TCNT) in TMR_X is set to count the internal clock pulses and to be cleared on
the rising edge of the external reset signal (IHI signal). The value to be used as the threshold for
deciding the pulse width is written in TCORB. The PWM decoder contains a delay latch which
uses the IHI signal as data and compare-match signal B (CMB) as a clock, and the state of the IHI
signal (the result of the pulse width decision) at the first compare-match signal B timing after
TCNT is reset by the rise of the IHI signal is output as the PDC signal.
The pulse width setting using TICRR and TICRF of TMR_X can be used to determine the pulse
width decision threshold. Examples of TCR and TCORB settings of TMR_X are shown in tables
13.4 and 13.5, and the PWM decoding timing chart is shown in figure 13.2.
Table 13.4 Examples of TCR Settings
Bit
7
6
5
4 and 3
Abbreviation
Contents
CMIEB
0
CMIEA
0
OVIE
0
CCLR1 and CCLR0 11
2 to 0
CKS2 to CKS0
001
Description
Interrupts due to compare-match and overflow are
disabled
TCNT is cleared by the rising edge of the external
reset signal (IHI signal)
Incremented on internal clock (ø)
Table 13.5 Examples of TCORB (Pulse Width Threshold) Settings
H'07
H'0F
H'1F
H'3F
H'7F
ø: 10 MHz
0.8 µs
1.6 µs
3.2 µs
6.4 µs
12.8 µs
ø: 12 MHz
0.67 µs
1.33 µs
2.67 µs
5.33 µs
10.67 µs
ø: 16 MHz
0.5 µs
1 µs
2 µs
4 µs
8 µs
ø: 20 MHz
0.4 µs
0.8 µs
1.6 µs
3.2 µs
6.4 µs
Rev. 2.0, 08/02, page 309 of 788