HD64F2145 Datasheet, PDF (639/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Write pulse application subroutine
Sub-Routine Write Pulse
WDT enable
Set PSU bit in FLMCR2
Wait ( ) µs
Set P bit in FLMCR1
Wait (z1) µs, (z2) µs or (z3) µs
*5
Clear P bit in FLMCR1
Wait ( ) µs
Start of programming
START
Set SWE bit in FLMCR1
Wait (x) µs
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Store 128-byte program data in program
data area and reprogram data area
*4
n=1
m=0
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
*1
Sub-Routine-Call
Apply write pulse z1 µs or z2 µs
See Note 7 for pulse width
Clear PSU bit in FLMCR2
Wait ( ) µs
Set PV bit in FLMCR1
Wait ( ) µs
Disable WDT
H'FF dummy write to verify address
Wait ( ) µs
n¬n+1
End Sub
Read verify data
*2
Note 7: Write Pulse Width
Number of Writes n
1
2
3
4
5
6
7
8
9
10
11
12
13
Write Time (z) µs
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
Increment address
Write data =
NG
verify data?
OK
NG
6≥n?
OK
Additional-programming data computation
m=1
Transfer additional-programming data to
additional-programming data area
*4
Reprogram data computation
*3
Transfer reprogram data to reprogram data area *4
128-byte
NG
data verification completed?
998
z2
999
z2
1000
z2
Note: Use a z3 µs write pulse for additional programming.
OK
Clear PV bit in FLMCR1
Wait ( ) µs
NG
6 ≥ n?
RAM
Program data storage
area (128 bytes)
OK
Successively write 128-byte data from additional-
programming data area in RAM to flash memory ^*1
Apply write pulse (Additional programming) *³
µs
Reprogram data storage
area (128 bytes)
m=0?
NG
NG
n ≥ (N)?
Additional-programming
data storage area
(128 bytes)
OK
Clear SWE bit in FLMCR1
Wait ( ) µs
OK
Clear SWE bit in FLMCR1
Wait ( ) µs
End of programming
Programming failure
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if
writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. Even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG.
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
5. A write pulse of z1 µs or z2 µs is applied according to the progress of the programming operation. See Note7 for details of the pulse widths. When writing of
additional-programming data is executed, a z3 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
6. The values of x, y, z1, z2, z3, , , , , , , and N are shown in section 28, Flash Memory Characteristics.
Reprogram Data Computation Table
Original Data
(D)
Verify Data
(V)
Reprogram Data
(X)
0
0
1
Comments
Programming completed
0
1
1
0
0
Programming incomplete;
reprogram
1
Additional-Programming Data Computation Table
Reprogram Data Verify Data
Additional-
(X')
(V)
Programming Data (Y)
Comments
0
0
0
1
0
Additional programming
to be executed
1
Additional programming
not to be executed
1
0
1
1
1
1
Still in erased state; no action
1
1
1
Additional programming
not to be executed
Figure 23.11 Program/Program-Verify Flowchart
Rev. 2.0, 08/02, page 599 of 788