HD64F2145 Datasheet, PDF (158/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 6.2 shows the bus specifications for the basic bus interface of each area.
Table 6.2 Bus Specifications for Basic Bus Interface
ABW
0
AST
0
1
WMS1
—
0
—*
WMS0
—
1
—*
WC1
—
—
0
1
1
0
—
—
—
1
0
1
—
—*
—*
0
1
Note:* Other than WMS1 = 0 and WMS0 = 1
WC0
—
—
0
1
0
1
—
—
0
1
0
1
Bus Specifications
Bus Width
Number of
Access
States
Number of
Program
Wait
States
16
2
0
16
3
0
3
0
1
2
3
8
2
0
8
3
0
3
0
1
2
3
6.4.2 Advanced Mode
The external address space is initialized as the basic bus interface and a 3-state access space. In
on-chip ROM enable extended mode, the address space other than on-chip ROM, on-chip RAM,
internal I/O registers, and their reserved areas is specified as the external address space. The on-
chip RAM and its reserved area are enabled when the RAME bit in SYSCR is set to 1. The on-
chip RAM and its reserved area are disabled and corresponding addresses are the external address
space when the RAME bit is cleared to 0.
6.4.3 Normal Mode
The external address space is initialized as the basic bus interface and a 3-state access space. In
on-chip ROM disable extended mode, the address space other than on-chip RAM and internal I/O
registers is specified as the external address space. In on-chip ROM enable extended mode, the
address space other than on-chip ROM, on-chip RAM, internal I/O registers, and their reserved
areas is specified as the external address space. The on-chip RAM area is enabled when the
Rev. 2.0, 08/02, page 118 of 788