HD64F2145 Datasheet, PDF (763/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 28.22 Bus Timing (2) (Advanced Mode)
Condition A:
V_CC = 5.0 V ± 10 %, V_CCB = 5.0 V ± 10 %, V_SS = 0 V, ø = 2 MHz to
maximum operating frequency, T_a = –20 to +75°C (normal specification
product), T_a = –40 to +85°C (wide range temperature specification product)
Condition B:
V_CC = 4.0 V to 5.5 V, V_CCB = 4.0 V to 5.5 V, V_SS = 0 V, ø = 2 MHz to
maximum operating frequency, T_a = –20 to +75°C (normal specification
product), T_a = –40 to +85°C (wide range temperature specification product)
Condition C:
V_CC = 2.7 V to 3.6 V, V_CCB = 2.7 V to 5.5 V, V_SS = 0 V, ø = 2 MHz to
maximum operating frequency, T_a = –20 to +75°C
Condition A Condition B Condition C
Item
10 MHz
Symbol Min Max
16 MHz
20 MHz
Test
Min Max Min Max Unit Conditions
Address delay time t
AD
Address setup time t_AS
—
60
0.5 × t_cyc —
– 50
— 45
0.5 × —
t_cyc –
35
—
30
0.5 × t_cyc —
– 25
ns Figures
ns ^{28.11 to}
28.15
Address hold time t
AH
0.5
×
t
cyc
—
– 20
0.5 × —
0.5
×
t
cyc
—
ns
t_cyc –
– 10
15
&6 delay time (,26) t_CSD
$6 delay time
t_ASD
5' delay time 1
t_RSD1
5' delay time 2
t_RSD2
Read data setup t
RDS
time
—
60
—
60
—
60
—
60
35
—
— 45 —
— 45 —
— 45 —
— 45 —
20 — 15
30 ns
30 ns
30 ns
30 ns
— ns
Read data hold time t_RDH
0
—
0 —0
— ns
Read data access t_ACC1
—
1.0 × t_cyc — 1.0 × —
1.0 × ns
time 1
– 80
t–
cyc
t–
cyc
55
40
Read data access t
ACC2
—
1.5
×
t
cyc
—
2.5 × —
2.5 × ns
time 2
– 50
t_cyc –
t_cyc –
35
25
Read data access t_ACC3
—
2.0 × t_cyc — 3.0 × —
3.0 × ns
time 3
– 80
t–
cyc
t–
cyc
55
40
Rev. 2.0, 08/02, page 723 of 788