HD64F2145 Datasheet, PDF (667/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

26.5 Software Standby Mode
The CPU makes a transition to software standby mode when the SLEEP instruction is executed
while the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is cleared to 0, and the PSS
bit in TCSR (WDT_1) is cleared to 0.
In software standby mode, the CPU, on-chip peripheral modules, and clock pulse generator all
stop. However, the contents of the CPU’s internal registers, on-chip RAM data, I/O ports, and the
states of on-chip peripheral modules other than the SCI, PWM, and PWMX, are retained as long
as the prescribed voltage is supplied.
Software standby mode is cleared by an external interrupt (NMI, IRQ0 to IRQ2, IRQ6, or IRQ7),
the 5(6 pin input, or 67%< pin input.
When an external interrupt request signal is input, system clock oscillation starts, and after the
elapse of the time set in bits STS2 to STS0 in SBYCR, software standby mode is cleared, and
interrupt exception handling is started. When clearing software standby mode with an IRQ0 to
IRQ2, IRQ6, or IRQ7 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt
with a higher priority than interrupts IRQ0 to IRQ2, IRQ6, and IRQ7 is generated. Software
standby mode cannot be cleared if an interrupt enable bit corresponding to an IRQ0 to IRQ2,
IRQ6, or IRQ7 interrupt is cleared to 0 or if the interrupt has been masked on the CPU side.
When the 5(6 pin is driven low, system clock oscillation is started. At the same time as system
clock oscillation starts, the system clock is supplied to the entire LSI. Note that the 5(6 pin must
be held low until clock oscillation stabilizes. When the 5(6 pin goes high after clock oscillation
stabilizes, the CPU begins reset exception handling.
When the 67%< pin is driven low, software standby mode is cancelled and a transition is made to
hardware standby mode.
Figure 26.3 shows an example in which a transition is made to software standby mode at the
falling edge of the NMI pin, and software standby mode is cleared at the rising edge of the NMI
pin.
In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Software standby mode is then cleared at the rising edge of the NMI pin.
Rev. 2.0, 08/02, page 627 of 788