HD64F2145 Datasheet, PDF (296/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

If ICRA to ICRAD are read when the corresponding input capture signal arrives, the internal input
capture signal is delayed by one system clock (ø). Figure 11.8 shows the timing for this case.
Read cycle of ICRA to ICRD
T1
T2
ø
Input capture
input pin
Input capture signal
Figure 11.8 Input Capture Input Signal Timing (When ICRA to ICRD are Read)
11.5.5 Buffered Input Capture Input Timing
ICRC and ICRD can operate as buffers for ICRA and ICRB, respectively. Figure 11.9 shows how
input capture operates when ICRC is used as ICRA's buffer register (BUFEA = 1) and IEDGA and
IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and IEDGC = 0),
so that input capture is performed on both the rising and falling edges of FTIA.
ø
FTIA
Input capture
signal
FRC
n
n+1
N
N+1
ICRA
M
n
nN
ICRC
m
M
Mn
Figure 11.9 Buffered Input Capture Timing
Even when ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected
transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge
transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and
if the ICICE bit is set at this time, an interrupt will be requested. The FRC value will not be
transferred to ICRC, however. In buffered input capture, if either set of two registers to which data
Rev. 2.0, 08/02, page 256 of 788