HD64F2145 Datasheet, PDF (318/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit Bit Name Initial Value R/W Description
1
OS1
0
R/W Output Select 1, 0
0
OS0
0
R/W These bits specify how the TMO1 pin output level is to be
changed by compare-match A of TCORA_1 and
TCNT_1.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
Note:* Only 0 can be written, for flag clearing.
• TCSR_Y
Bit Bit Name Initial Value R/W Description
7
CMFB 0
R/(W)*¹ Compare-Match Flag B
[Setting condition]
When the values of TCNT_Y and TCORB_Y match
[Clearing conditions]
• Read CMFB when CMFB = 1, then write 0 in CMFB
6
CMFA 0
• When the DTC is activated by a CMIB interrupt
R/(W)*¹ Compare-Match Flag A
[Setting condition]
When the values of TCNT_Y and TCORA_Y match
[Clearing conditions]
• Read CMFA when CMFA = 1, then write 0 in CMFA
5
OVF
0
• When the DTC is activated by a CMIA interrupt
R/(W)*¹ Timer Overflow Flag
[Setting condition]
When TCNT_Y overflows from H'FF to H'00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
4
ICIE
0
R/W Input Capture Interrupt Enable
Enables or disables the ICF interrupt request (ICIX) when
the ICF bit in TCSR_X is set to 1.
0: ICF interrupt request (ICIX) is disabled
1: ICF interrupt request (ICIX) is enabled
Rev. 2.0, 08/02, page 278 of 788