HD64F2145 Datasheet, PDF (732/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Condition
10 MHz
Item
Symbol Min
Max
SCI
Transmit data delay time
t
—
100
TXD
(synchronous)
Receive data setup time
(synchronous)
t
100
—
RXS
Receive data hold time
(synchronous)
t_RXH
100
—
A/D
Trigger input setup time
converter
t
50
—
TRGS
WDT 5(62 output delay time
t_RESD
—
200
5(62 output pulse width
t_RESOW
132
—
Note:* Only peripheral modules that can be used in subclock operation
Unit Test Conditions
ns Figure 28.24
ns
ns
ns Figure 28.25
ns Figure 28.26
t_cyc
Table 28.8 Timing of On-Chip Peripheral Modules (2)
Condition: V_CC = 2.7 V to 3.6 V, V_CCB = 2.7 V to 5.5 V, V_SS = 0 V, ø = 2 MHz to maximum
operating frequency, T_a = –20 to +75°C
Item
Symbol
XBS read &6/HA0 setup time
t
HAR
cycle
&6/HA0 hold time
t_HRA
,25 pulse width
t
HRPW
HDB delay time
t_HRD
HDB hold time
t
HRF
HIRQ delay time
t
HIRQ
XBS write &6/HA0 setup time
t_HAW
cycle
&6/HA0 hold time
t
HWA
,2: pulse width
t_HWPW
HDB setup
Fast A20 gate not
t
HDW
time
used
Fast A20 gate
used
HDB hold time
t
HWD
GA20 delay time
t_HGA
Condition
10 MHz
Min
Max
10
—
10
—
220
—
—
200
0
40
—
200
10
—
10
—
100
—
50
—
85
—
25
—
—
180
Unit Test Conditions
ns Figure 28.27
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 2.0, 08/02, page 692 of 788