HD64F2145 Datasheet, PDF (671/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

26.9 Subactive Mode
The CPU makes a transition to subactive mode when the SLEEP instruction is executed in high-
speed mode with the SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR set
to 1, and the PSS bit in TCSR (WDT_1) set to 1. When an interrupt occurs in watch mode, and if
the LSON bit in LPWRCR is 1, a direct transition is made to subactive mode. Similarly, if an
interrupt occurs in subsleep mode, a transition is made to subactive mode.
In subactive mode, the CPU operates at a low speed based on the subclock and sequentially
executes programs. Peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 are
also stopped.
When operating the CPU in subactive mode, the SCK2 to SCK0 bits in SBYCR must be cleared to
0.
Subactive mode is exited by the SLEEP instruction, 5(6 pin input, or 67%< pin input.
When the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the DTON bit in
LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1, the CPU exits subactive mode
and a transition is made to watch mode. When the SLEEP instruction is executed with the SSBY
bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1)
set to 1, a transition is made to subsleep mode. When the SLEEP instruction is executed with the
SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR set to 10, and the PSS bit
in TCSR (WDT_1) set to 1, a direct transition is made to high-speed mode.
For details of direct transitions, see section 26.11, Direct Transitions.
When the 5(6 pin is driven low, system clock oscillation starts. Simultaneously with the start of
system clock oscillation, the system clock is supplied to the entire LSI. Note that the 5(6 pin must
be held low until the clock oscillation is stabilized. If the 5(6 pin is driven high after the clock
oscillation stabilization time has passed, the CPU begins reset exception handling.
If the 67%< pin is driven low, the LSI enters hardware standby mode.
Rev. 2.0, 08/02, page 631 of 788