HD64F2145 Datasheet, PDF (300/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

ø
FRC
N
N+1
ICRD + OCRDM × 2
N
Compare-match
signal
Input capture
mask signal
Figure 11.16 Timing of Input Capture Mask Signal Clearing
11.6 Interrupt Sources
The free-running timer can request seven interrupts: ICIA to ICID, OCIA, OCIB, and FOVI. Each
interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the
interrupt controller for each interrupt. Table 11.2 lists the sources and priorities of these interrupts.
The ICIA, ICIB, OCIA, and OCIB interrupts can be used as the on-chip DTC activation sources.
Table 11.2 FRT Interrupt Sources
Interrupt
ICIA
ICIB
ICIC
ICID
OCIA
OCIB
FOVI
Interrupt Source
Interrupt Flag
Input capture of ICRA
ICFA
Input capture of ICRB
ICFB
Input capture of ICRC
ICFC
Input capture of ICRD
ICFD
Compare match of OCRA OCFA
Compare match of OCRB OCFB
Overflow of FRC
OVF
DTC
Activation
Enabled
Enabled
Disabled
Disabled
Enabled
Enabled
Disabled
Priority
High
Low
Rev. 2.0, 08/02, page 260 of 788