HD64F2145 Datasheet, PDF (403/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Initialization
Start transmission
Read TDRE flag in SSR
TDRE = 1
Yes
Write transmit data to TDR
and clear TDRE flag in SSR to 0
All data transmitted?
Yes
Read TEND flag in SSR
TEND = 1
Yes
Break output?
Yes
Clear DR to 0 and
set DDR to 1
[1]
[2]
No
No
[3]
No
No
[4]
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a frame
of 1s is output, and transmission is
enabled.
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR, and clear
the TDRE flag to 0. However, the
TDRE flag is checked and cleared
automatically when the DTC is
initiated by a transmit data empty
interrupt (TXI) request and writes
data to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set DDR for the port
corresponding to the TxD pin to 1,
clear DR to 0, then clear the TE bit
in SCR to 0.
Clear TE bit in SCR to 0
<End>
Figure 15.7 Sample Serial Transmission Flowchart
Rev. 2.0, 08/02, page 363 of 788