HD64F2145 Datasheet, PDF (105/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

3.2.2 System Control Register (SYSCR)
SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode
and the detection edge for NMI, pin location selection, enables or disables register access to the
on-chip peripheral modules, and enables or disables on-chip RAM address space.
Bit Bit Name Initial Value R/W Description
7 CS2E
0
R/W Chip Select 2 Enable
Specifies the location of the control pin (&65) of the
host interface together with the FGA20E bit in HICR.
See section 18, Host Interface X-Bus Interface (XBS),
for details.
6 IOSE
0
R/W IOS Enable
Enables or disables $6/,26 pin function in extended
mode.
0: $6 pin
Outputs low when an external area is accessed.
1: ,26 pin
Outputs low when a specified address of addresses
H’(FF)F000 to H’(FF)F7FF is accessed.
5 INTM1
0
4 INTM0
0
R
These bits select the control mode of the interrupt
R/W ^{controller. For details on the interrupt control modes}
and interrupt control select modes 1 and 0, see section
5.6, Interrupt Control Modes and Interrupt Operation.
00: Interrupt control mode 0
01: Interrupt control mode 1
10: Setting prohibited
11: Setting prohibited
3 XRST
1
R
External Reset
This bit indicates the reset source. A reset is caused by
an external reset input, or when the watchdog timer
overflows.
0: A reset is caused when the watchdog timer
overflows.
1: A reset is caused by an external reset.
Rev. 2.0, 08/02, page 65 of 788