HD64F2145 Datasheet, PDF (136/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

When pin ,549 is used as an IRQ6 interrupt input pin, clear the KMIMR6 bit to 0.
When pin ,54: is used as an IRQ7 interrupt pin, set all of bits KMIMR15 to KMIMR8 and
WUEMR7 to WUEMR0 to 1. If any of these bits is cleared to 0, IRQ7 interrupt input from the
,54: pin will be ignored.
Since interrupt request flags IRQ7F to IRQ0F are set each time the setting condition is satisfied,
regardless of the IER setting, refer to a needed flag only.
KIN15 to KIN0 Interrupts, WUE7 to WUE0 Interrupts: Interrupts KIN15 to KIN0 and WUE7
to WUE0 are requested by an input signal at pins .,148 to .,13 and :8(: to :8(3. When
pins .,148 to .,13 and :8(: to :8(3 are used for key-sense input or wakeup event, clear the
corresponding KMIMR and WUEMR bits to 0 in order to enable their key-sense input and
wakeup event interrupts. Remaining unused KMIMR and WUEMR bits for key-sense input
should be set to 1 in order to disable interrupts. Interrupts WUE7 to WUE0 and KIN15 to KIN8
generate IRQ7 interrupts, and interrupts KIN7 to KIN0 generate IRQ6 interrupts. The pin
conditions for interrupt request generation, enable of interrupt requests, settings of interrupt
control levels, and status display of interrupt requests depend on each setting and display of the
IRQ7 or IRQ6 interrupt.
When pins .,1: to .,13, .,148#to .,1;, or :8(: to :8(3 are used as key-sense interrupt
input pins or wakeup event interrupt input pins, either low-level sensing or falling-edge sensing
must be designated as the interrupt sense condition for the corresponding interrupt source (IRQ6
or IRQ7).
5.4.2 Internal Interrupts
Internal interrupts issued from the on-chip peripheral modules have the following features:
1. For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that individually select enabling or disabling of these interrupts. When the
enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt
controller.
2. The control level for each interrupt can be set by ICR.
3. The DTC can be activated by an interrupt request from an on-chip peripheral module.
4. An interrupt request that activates the DTC is not affected by the interrupt control mode or the
status of the CPU interrupt mask bits.
5.5 Interrupt Exception Handling Vector Table
Table 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. For
default priorities, the lower the vector number, the higher the priority. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed.
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