HD64F2145 Datasheet, PDF (286/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

11.3.6 Timer Interrupt Enable Register (TIER)
TIER enables and disables interrupt requests.
Bit Bit Name
7 ICIAE
6 ICIBE
5 ICICE
4 ICIDE
3 OCIAE
Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Input Capture Interrupt A Enable
Selects whether to enable input capture interrupt A
request (ICIA) when input capture flag A (ICFA) in
TCSR is set to 1.
0: ICIA requested by ICFA is disabled
1: ICIA requested by ICFA is enabled
Input Capture Interrupt B Enable
Selects whether to enable input capture interrupt B
request (ICIB) when input capture flag B (ICFB) in
TCSR is set to 1.
0: ICIB requested by ICFB is disabled
1: ICIB requested by ICFB is enabled
Input Capture Interrupt C Enable
Selects whether to enable input capture interrupt C
request (ICIC) when input capture flag C (ICFC) in
TCSR is set to 1.
0: ICIC requested by ICFC is disabled
1: ICIC requested by ICFC is enabled
Input Capture Interrupt D Enable
Selects whether to enable input capture interrupt D
request (ICID) when input capture flag D (ICFD) in
TCSR is set to 1.
0: ICID requested by ICFD is disabled
1: ICID requested by ICFD is enabled
Output Compare Interrupt A Enable
Selects whether to enable output compare interrupt A
request (OCIA) when output compare flag A (OCFA) in
TCSR is set to 1.
0: OCIA requested by OCFA is disabled
1: OCIA requested by OCFA is enabled
Rev. 2.0, 08/02, page 246 of 788