HD64F2145 Datasheet, PDF (145/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

5.6.4 Interrupt Response Times
Table 5.5 shows interrupt response times − the intervals between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The execution status
symbols used in table 5.5 are explained in table 5.6.
Table 5.5 Interrupt Response Times
No. Execution Status
Normal Mode
Advanced Mode
1 Interrupt priority determination*¹
3
2 Number of wait states until executing
instruction ends*²
1 to (19 + 2·SI)
3 PC, CCR stack save
2·SK
2·SK
4 Vector fetch
SI
2·SI
5 Instruction fetch*³
2·SI
6 Internal processing*⁴
2
Total (using on-chip memory)
11 to 31
12 to 32
Notes: 1. Two states in case of internal interrupt.
2. Refers to MULXS and DIVXS instructions.
3. Prefetch after interrupt acceptance and prefetch of interrupt handling routine.
4. Internal processing after interrupt acceptance and internal processing after vector fetch.
Table 5.6 Number of States in Interrupt Handling Routine Execution Status
Object of Access
External Device
8-Bit Bus
16-Bit Bus
Symbol
Internal
Memory
2-State 3-State 2-State
Access Access Access
3-State
Access
Instruction fetch SI
1
4
6 + 2m 2
3+m
Branch address read SJ
Stack manipulation SK
Legend
m: Number of wait states in external device access
Rev. 2.0, 08/02, page 105 of 788