HD64F2145 Datasheet, PDF (578/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

The timing of the /)5$0(, LCLK, and LAD signals is shown in figures 19.2 and 19.3.
LCLK
LAD3–LAD0
Start
ADDR TAR Sync Data TAR Start
Cycle type,
direction,
and size
Number of clocks ¹
1
4
2
1
2
2
1
Figure 19.2 Typical /)5$0( Timing
LCLK
LAD3–LAD0
Start
ADDR
Cycle type,
direction,
and size
TAR Sync
Slave must stop driving
Too many Syncs
cause timeout
Master will
drive high
Figure 19.3 Abort Mechanism
Rev. 2.0, 08/02, page 538 of 788