HD64F2145 Datasheet, PDF (313/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit Bit Name Initial Value R/W Description
4
CCLR1 0
R/W Counter Clear 1, 0
3
CCLR0 0
R/W These bits select the method by which the timer counter is
cleared.
00: Clearing is disabled
01: Cleared on compare-match A
10: Cleared on compare-match B
11: Cleared on rising edge of external reset input
2
CKS2 0
R/W Clock Select 2 to 0
1
CKS1 0
0
CKS0 0
R/W These bits select the clock input to TCNT and count
R/W ^{condition, together with the ICKS1 and ICKS0 bits in STCR.}
For details, see table 12.2.
Table 12.2 Clock Input to TCNT and Count Condition
Channel CKS2
TMR_0 0
0
0
0
0
0
0
1
TCR
CKS1 CKS0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
STCR
ICKS1 ICKS0
—
—
—
0
—
1
—
0
—
1
—
0
—
1
—
—
Description
Disables clock input
Increments at falling edge of internal clock
ø/8
Increments at falling edge of internal clock
ø/2
Increments at falling edge of internal clock
ø/64
Increments at falling edge of internal clock
ø/32
Increments at falling edge of internal clock
ø/1024
Increments at falling edge of internal clock
ø/256
Increments at overflow signal from
TCNT_1*
Rev. 2.0, 08/02, page 273 of 788