HD64F2145 Datasheet, PDF (729/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bus Timing: Table 28.7 shows the bus timing. Operation in external expansion mode is not
guaranteed when operating on the subclock (ø = 32.768 kHz).
Table 28.7 Bus Timing (1) (Normal Mode)
Conditions: V_CC = 2.7 V to 3.6 V, V_CCB = 2.7 V to 5.5 V, V_SS = 0 V, ø = 2 MHz to maximum
operating frequency, T_a = –20 to +75°C
Item
Address delay time
Address setup time
Address hold time
&6 delay time (,26)
$6 delay time
5' delay time 1
5' delay time 2
Read data setup time
Read data hold time
Read data access time 1
Read data access time 2
Read data access time 3
Read data access time 4
Read data access time 5
+:5, /:5 delay time 1
+:5, /:5 delay time 2
+:5, /:5 pulse width 1
+:5, /:5 pulse width 2
Write data delay time
Write data setup time
Write data hold time
:$,7 setup time
:$,7 hold time
Condition
10 MHz
Symbol Min
Max
t_AD
t_AS
t_AH
t_CSD
t
ASD
t_RSD1
t_RSD2
t_RDS
t_RDH
t
ACC1
t_ACC2
t_ACC3
t_ACC4
t_ACC5
t
WRD1
t
WRD2
t_WSW1
t_WSW2
t_WDD
t
WDS
t
WDH
t
WTS
t_WTH
—
0.5 × t_cyc – 30
0.5 × t_cyc – 20
—
—
—
—
35
0
—
—
—
—
—
—
—
1.0 × t_cyc – 40
1.5 × t_cyc – 40
—
0
20
60
10
40
—
—
40
60
60
60
—
—
1.0
×
t
cyc
–
60
1.5 × t_cyc – 50
2.0 × t_cyc – 60
2.5 × t_cyc – 50
3.0 × t_cyc – 60
60
60
—
—
60
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test
Conditions
Figures 28.11
to 28.15
Rev. 2.0, 08/02, page 689 of 788