HD64F2145 Datasheet, PDF (301/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

11.7 Usage Notes
11.7.1 Conflict between FRC Write and Clear
If an internal counter clear signal is generated during the state after an FRC write cycle, the clear
signal takes priority and the write is not performed. Figure 11.17 shows the timing for this type of
conflict.
Write cycle of FRC
T1
T2
Ø
Address
FRC address
Internal write signal
Counter clear signal
FRC
N
H'0000
Figure 11.17 FRC Write-Clear Conflict
Rev. 2.0, 08/02, page 261 of 788