HD64F2145 Datasheet, PDF (628/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

23.5.2 Flash Memory Control Register 2 (FLMCR2)
FLMCR2 monitors the state of flash memory programming/erasing protection (error protection)
and sets up the flash memory to transit to programming/erasing mode. FLMCR2 is initialized to
H’00 by a reset or in hardware standby mode. The ESU and PSU bits are cleared to 0 in software
standby mode, sub-active mode, sub-sleep mode, or watch mode, or when the SWE bit in
FLMCR1 is cleared to 0.
Bit Bit Name
7 FLER
6 to —
2
1 ESU
0 PSU
Initial Value
0
All 0
0
0
R/W
R
R/(W)
R/W
R/W
Description
Flash memory error
Indicates that an error has occurred during flash
memory programming/erasing. When this bit is set
to 1, flash memory goes to the error-protection state.
For details, see section 23.9.3, Error Protection.
Reserved
The initial values should not be modified.
Erase Setup
When this bit is set to 1 while SWE = 1, the flash
memory transits to the erase setup state. When it is
cleared to 0, the erase setup state is cancelled. Set
this bit to 1 before setting the E bit in FLMCR1 to 1.
Program Setup
When this bit is set to 1 while SWE = 1, the flash
memory transits to the program setup state. When it
is cleared to 0, the program setup state is cancelled.
Set this bit to 1 before setting the P bit in FLMCR1 to
1.
23.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2)
EBR1 and EBR2 are used to specify the flash memory erase block. EBR1 and EBR2 are
initialized to H’00 by a reset, or in hardware standby mode, software standby mode, sub-active
mode, sub-sleep mode, or watch mode, or when the SWE bit in FLMCR1 is cleared to 0. Set only
one bit to 1 at a time, otherwise all bits in EBR1 and EBR2 are automatically cleared to 0.
• EBR1 (64-kbyte version)
Bit
7 to 0
Bit Name
—
Initial Value
All 0
R/W
R/(W)
Description
Reserved
The initial values should not be modified.
Rev. 2.0, 08/02, page 588 of 788