HD64F2145 Datasheet, PDF (653/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 25.4 External Clock Output Stabilization Delay Time
Condition: V_CC = 2.7 V to 5.5 V, AV_CC = 2.7 V to 5.5 V, V_SS = AV_SS = 0 V
Item
Symbol
External clock output stabilization
delay time
t_DEXT*
Note:*
t
DEXT
includes
a
5(6
pulse
width
(t ).
RESW
Min.
500
Max.
—
Unit
µs
Remarks
Figure 25.6
VCC ^{2.7 V}
VIH
EXTAL
ø
(Internal and external)
tDEXT*
Note:* The external clock output stabilization delay time (tDEXT) includes a
pulse width (tRESW).
Figure 25.6 Timing of External Clock Output Stabilization Delay Time
25.2 Duty Correction Circuit
The duty correction circuit is valid when the oscillating frequency is 5 MHz or more. It corrects
the duty of a clock that is output from the oscillator, and generates the system clock (ø).
25.3 Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock (ø), and generates ø/2, ø/4, ø/8, ø/16,
and ø/32 clocks.
Rev. 2.0, 08/02, page 613 of 788