HD64F2145 Datasheet, PDF (336/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Timing of Switchover
by Means of CKS1
No. and CKS0 Bits
TCNT Clock Operation
3
Clock switching from high
to low level∗³
Clock before
switchover
Clock after
switchover
*⁴
TCNT
clock
TCNT
4
Clock switching from high
to high level
Clock before
switchover
Clock after
switchover
TCNT
clock
N
N+1
N+2
CKS bit rewrite
TCNT
N
N+1
N+2
CKS bit rewrite
Notes: 1. Includes switching from low to stop, and from stop to low.
2. Includes switching from stop to high.
3. Includes switching from high to stop.
4. Generated on the assumption that the switchover is a falling edge; TCNT is
incremented.
12.9.6 Mode Setting with Cascaded Connection
If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock
pulses for TCNT_0 and TCNT_1 are not generated, and thus the counters will stop operating.
Simultaneous setting of these two modes should therefore be avoided.
12.9.7 Module Stop Mode Setting
TMR operation can be enabled or disabled using the module stop control register. The initial
setting is for TMR operation to be halted. Register access is enabled by canceling the module stop
mode. For details, refer to section 26, Power-Down Modes.
Rev. 2.0, 08/02, page 296 of 788