HD64F2145 Datasheet, PDF (565/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

R/W
Bit Bit Name Initial Value Slave Host Description
0 OBF3A 0
R/(W)* R Output Buffer Full
Set to 1 when the slave processor (this LSI) writes to
ODR. OBF3A is cleared to 0 when the host
processor reads ODR.
0: [Clearing condition]
When the host processor reads ODR using I/O read
cycle, or the slave processor writes 0 to the OBF bit
1: [Setting condition]
When the slave processor writes to ODR
Note:* Only 0 can be written to clear the flag.
• STR3 (TWRE = 0 and SELSTR3 = 1)
R/W
Bit Bit Name Initial Value Slave Host Description
7 DBU37 0
R/W R Defined by User
6 DBU36 0
R/W R The user can use these bits as necessary.
5 DBU35 0
R/W R
4 DBU34 0
R/W R
3 C/'3
0
R
R Command/Data
When the host processor writes to an IDR register,
bit 2 of the I/O address is written into this bit to
indicate whether IDR contains data or a command.
0: Contents of data register (IDR) are data
1: Contents of data register (IDR) are a command
2 DBU32 0
R/W R Defined by User
The user can use this bit as necessary.
Rev. 2.0, 08/02, page 525 of 788