HD64F2145 Datasheet, PDF (652/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 25.3 External Clock Input Conditions
Item
External clock input
pulse width low level
External clock input
pulse width high level
External clock rising time
External clock falling
time
Clock pulse width low
level
Clock pulse width high
level
Symbol
t
EXL
t
EXH
t_EXr
t_EXf
t_CL
t_CH
V_CC = 2.7
to 3.6 V
Min Max
40 —
40 —
— 10
— 10
0.4 0.6
80 —
0.4 0.6
80 —
V_CC = 5.0 V
± 10 %
Min Max
20 —
20 —
—5
—5
0.4 0.6
80 —
0.4 0.6
80 —
Unit
ns
ns
ns
ns
t_cyc
ns
t_cyc
ns
Test Conditions
Figure 25.5
ø ≥ 5 MHz
ø < 5 MHz
ø ≥ 5 MHz
ø < 5 MHz
Figure
28.6
EXTAL
t_EXH
t_EXL
V_CC × 0.5
t_EXr
t_EXf
Figure 25.5 External Clock Input Timing
The oscillator and duty correction circuit have a function to adjust the waveform of the external
clock input that is input to the EXTAL pin. When a specified clock signal is input to the EXTAL
pin, internal clock signal output is determined after the external clock output stabilization delay
time (t_DEXT) has passed. As the clock signal output is not determined during the t_DEXT cycle, a reset
signal should be set to low to hold it in reset state. Table 25.4 shows the external clock output
stabilization delay time. Figure 25.6 shows the timing of the external clock output stabilization
delay time.
Rev. 2.0, 08/02, page 612 of 788