HD64F2145 Datasheet, PDF (322/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

12.3.9 Timer Input Select Register (TISR)
TISR selects a signal source of external clock/reset input for the counter.
Bit Bit Name Initial Value R/W Description
7
—
All 1
to
1
R/(W) Reserved
The initial values should not be modified.
0
IS
0
R/W Input Select
Selects an internal synchronization signal (IVG signal) or
timer clock/reset input pin VSYNCI/TMIY (TMCIY/TMRIY)
as the signal source of external clock/reset input for the
TMR_Y counter.
0: IVG signal is selected
1: VSYNCI/TMIY (TMCIY/TMRIY) is selected
12.4 Operation
12.4.1 Pulse Output
Figure 12.3 shows an example for outputting an arbitrary duty pulse.
1. Clear the CCLR1 bit in TCR to 0 so that TCNT is cleared according to the compare match of
TCORA, and then set the CCLR0 bit to 1.
2. Set the OS3 to OS0 bits in TCSR to B'0110 so that 1 is output according to the compare match
of TCORA and 0 is output according to the compare match of TCORB.
According to the above settings, the waveforms with the TCORA cycle and TCORB pulse width
can be output without the intervention of software.
H'FF
TCORA
TCORB
H'00
TMO
TCNT
Counter clear
Figure 12.3 Pulse Output Example
Rev. 2.0, 08/02, page 282 of 788