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HD64F2145 Datasheet, PDF (81/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer
2.6 Instruction Set
The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as
shown in table 2.1.
Table 2.1 Instruction Classification
Function
Instructions
Size Types
Data transfer
MOV
POP*1, PUSH*1
LDM*5, STM*5
MOVFPE*3, MOVTPE*3
B/W/L 5
W/L
L
B
Arithmetic
operations
ADD, SUB, CMP, NEG
ADDX, SUBX, DAA, DAS
B/W/L 19
B
INC, DEC
B/W/L
ADDS, SUBS
L
MULXU, DIVXU, MULXS, DIVXS
B/W
EXTU, EXTS
W/L
TAS*4
B
Logic operations AND, OR, XOR, NOT
B/W/L 4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
ROTXR
B/W/L 8
Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, B
14
BIAND, BOR, BIOR, BXOR, BIXOR
Branch
BCC*2, JMP, BSR, JSR, RTS
—
5
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, —
9
NOP
Block data transfer EEPMOV
—
1
Total: 65
Notes: B: Byte size; W: Word size; L: Longword size.
1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-
SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,
@-SP.
2. B is the general name for conditional branch instructions.
CC
3. Cannot be used in this LSI.
4. When using the TAS instruction, use registers ER0, ER1, ER4, and ER5.
5. ER7 is not used as the register that can be saved (STM)/restored (LDM) when using
STM/LDM instruction, because ER7 is the stack pointer.
Rev. 2.0, 08/02, page 41 of 788