HD64F2145 Datasheet, PDF (444/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

16.3.5 I²C Bus Control Register (ICCR)
ICCR controls the I²C bus interface and performs interrupt flag confirmation.
Bit Bit Name Initial Value R/W
7 ICE
0
R/W
6 IEIC
0
R/W
5 MST
0
R/W
4 TRS
0
R/W
Description
I²C Bus Interface Enable
0: I²C bus interface modules are stopped and I²C bus
interface module internal state is initialized. SAR and SARX
can be accessed.
1: I²C bus interface modules can perform transfer
operation, and the ports function as the SCL and SDA
input/output pins. ICMR and ICDR can be accessed.
I²C Bus Interface Interrupt Enable
0: Disables interrupts from the I²C bus interface to the CPU
1: Enables interrupts from the I²C bus interface to the CPU.
Master/Slave Select
Transmit/Receive Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both these bits will be cleared by hardware when they lose
in a bus contention in master mode with the I²C bus format.
In slave receive mode with I²C bus format, the R/W bit in
the first frame immediately after the start condition sets
these bits in receive mode or transmit mode automatically
by hardware.
Modification of the TRS bit during transfer is deferred until
transfer is completed, and the changeover is made after
completion of the transfer.
Rev. 2.0, 08/02, page 404 of 788