HD64F2145 Datasheet, PDF (545/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

19.2 Input/Output Pins
Table 19.1 lists the input and output pins of the LPC module.
Table 19.1 Pin Configuration
Name
Abbreviation Port
I/O
Function
LPC address/
data 3 to 0
LPC frame
LPC reset
LAD3 to LAD0 P33 to P30 Input/
output
/)5$0(
P34
Input*¹
/5(6(7
P35
Input*¹
Serial (4-signal-line) transfer cycle
type/address/data signals,
synchronized with LCLK
Transfer cycle start and forced
termination signal
LPC interface reset signal
LPC clock
LCLK
P36
Input
33 MHz PCI clock signal
Serialized interrupt SERIRQ
P37
request
LSCI general
LSCI
PB1
output
LSMI general
/60,
PB0
output
PME general
30(
P80
output
GATE A20
GA20
P81
Input/
output*¹
Output*^1, *²
Serialized host interrupt request
signal, synchronized with LCLK
(SMI, IRQ1, IRQ6, IRQ9 to IRQ12)
General output
Output*^1, *² General output
Output*^1, *² General output
Output*^1, *² A20 gate control signal output
LPC clock run
&/.581
P82
LPC power-down /3&3'
P83
Input/
output*^1, *²
Input*¹
LCLK restart request signal in case
of serial host interrupt request
LPC module shutdown signal
Notes: 1. Pin state monitoring input is possible in addition to the LPC interface control
input/output function.
2. Only 0 can be output. If 1 is output, the pin goes to the high-impedance state, so an
external resistor is necessary to pull the signal up to V_CC.
Rev. 2.0, 08/02, page 505 of 788