HD64F2145 Datasheet, PDF (464/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

16.4 Operation
The I²C bus interface has an I²C bus format and a serial format.
16.4.1 I²C Bus Data Format
The I²C bus format is an addressing format with an acknowledge bit. This is shown in figure 16.3.
The first frame following a start condition always consists of 9 bits.
IIC_0 only is capable of formatless operation, as shown in figure 16.4.
The serial format is a non-addressing format with no acknowledge bit. This is shown in figure
16.5.
Figure 16.6 shows the I²C bus timing.
The symbols used in figures 16.3 to 16.6 are explained in table 16.6.
(a) FS = 0 or FSX = 0
S
SLA
R/
A
1
7
11
1
DATA
n
A
1
m
(b) Start condition retransmission FS = 0 or FSX = 0
S
SLA
R/
A
DATA
A/ S
1
7
11
n1
11
1
m1
A/ P Transfer bit count
1
1 ^{(n = 1 to 8)}
Transfer frame count
(m = from 1)
SLA R/ A
7
11
1
DATA
n2
m2
A/ P
11
Upper row: Transfer bit count (n1, n2 = 1 to 8)
Lower row: Transfer frame count (m1, m2 = from 1)
Figure 16.3 I²C Bus Data Format (I²C Bus Format)
FS = 0 or FSX = 0
DATA
A
DATA
A
A/
8
1
n
1
1
m
1 _{Transfer bit count}
(n = 1 to 8)
Transfer frame count
(m = from 1)
Note: * This mode is applied to the PC monitor system standard DDC (Display Data Channel).
Figure 16.4 I²C Bus Data Format (Formatless) (IIC_0 Only)
Rev. 2.0, 08/02, page 424 of 788