HD64F2145 Datasheet, PDF (332/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

12.9.2 Conflict between TCNT Write and Increment
If a TCNT input clock is generated during the T2 state of a TCNT write cycle as shown in figure
12.15, the write takes priority and the counter is not incremented.
TCNT write cycle by CPU
T1
T2
Ø
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 12.15 Conflict between TCNT Write and Increment
Rev. 2.0, 08/02, page 292 of 788