HD64F2145 Datasheet, PDF (161/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Byte size
Byte size
· Even address
· Odd address
Upper data bus Lower data bus
D15
D8 D7
D0
Word size
Longword
size
1st bus cycle
2nd bus cycle
Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space)
6.5.2 Valid Strobes
Table 6.4 shows the data buses used and valid strobes for each access space.
In a read, the 5' signal is valid for both the upper and lower halves of the data bus. In a write, the
+:5 signal is valid for the upper half of the data bus, and the /:5 signal for the lower half.
Table 6.4 Data Buses Used and Valid Strobes
Area
Access Read/
Valid
Size
Write Address Strobe
Upper Data Bus Lower Data
(D15 to D8)
Bus (D7 to D0)
8-bit
Byte
Read —
5'
Valid
Ports or others
access space
Write —
+:5
Ports or others
16-bit
Byte
Read Even
5'
Valid
Invalid
access space
Odd
Invalid
Valid
Write Even
+:5
Valid
Undefined
Odd
/:5
Undefined
Valid
Word Read —
5'
Valid
Valid
Write —
+:5, /:5 Valid
Valid
Note:* Undefined: Undefined data is output.
Invalid: Input state with the input value ignored.
Ports or others: Used as ports or I/O pins for on-chip peripheral modules, and are not used
as the data bus.
Rev. 2.0, 08/02, page 121 of 788