HD64F2145 Datasheet, PDF (761/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bus Timing: Table 28.22 shows the bus timing. Operation in external expansion mode is not
guaranteed when operating on the subclock (ø = 32.768 kHz).
Table 28.22 Bus Timing (1) (Normal Mode)
Condition A:
V_CC = 5.0 V ± 10%, V_CCB = 5.0 V ± 10%, V_SS = 0 V, ø = 2 MHz to maximum
operating frequency, T_a = –20 to +75°C (normal specification product), T_a =
–40 to +85°C (wide range temperature specification product)
Condition B:
V_CC = 4.0 V to 5.5 V, V_CCB = 4.0 V to 5.5 V, V_SS = 0 V, ø = 2 MHz to
maximum operating frequency, T_a = –20 to +75°C (normal specification
product), T_a = –40 to +85°C (wide range temperature specification product)
Condition C:
V_CC = 2.7 V to 3.6 V, V_CCB = 2.7 V to 5.5 V, V_SS = 0 V, ø = 2 MHz to
maximum operating frequency, T_a = –20 to +75°C
Item
Symbol
Address delay time t
AD
Address setup time t_AS
Address hold time t
AH
&6 delay time (,26) t_CSD
$6 delay time
t_ASD
5' delay time 1
t_RSD1
5' delay time 2
t
RSD2
Read data setup t
RDS
time
Read data hold time t_RDH
Read data access t_ACC1
time 1
Read data access t
ACC2
time 2
Condition A
10 MHz
Min Max
—
40
0.5 × —
tcyc –
30
0.5
×
t
cyc
—
– 20
—
40
—
60
—
60
—
60
35
—
0
—
—
1.0 ×
t–
cyc
60
—
1.5 ×
t_cyc –
50
Condition B
16 MHz
Min Max
—
30
0.5 × —
t_cyc –
20
0.5 × —
t–
cyc
15
—
30
—
45
—
45
—
45
20 —
Condition C
20 MHz
Min Max
—
20
0.5 × t_cyc —
– 15
0.5
×
t
cyc
—
– 10
—
20
—
30
—
30
—
30
15
—
Test
Unit Conditions
ns Figures
ns ^{28.11 to}
28.15
ns
ns
ns
ns
ns
ns
0
—0
—
1.0 × —
t–
cyc
40
—
1.5 × —
t_cyc –
35
— ns
1.0 × ns
t–
cyc
30
1.5 × ns
t_cyc –
25
Rev. 2.0, 08/02, page 721 of 788