HD64F2145 Datasheet, PDF (29/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Figure 15.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) ...........................................369
Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart.........................................370
Figure 15.12 Example of SCI Receive Operation
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)...............................371
Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1) ........................................372
Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) ........................................373
Figure 15.14 Data Format in Clocked Synchronous Communication (LSB-First) .....................374
Figure 15.15 Sample SCI Initialization Flowchart......................................................................375
Figure 15.16 Example of SCI Transmit Operation in Clocked Synchronous Mode ...................376
Figure 15.17 Sample Serial Transmission Flowchart..................................................................377
Figure 15.18 Example of SCI Receive Operation in Clocked Synchronous Mode.....................378
Figure 15.19 Sample Serial Reception Flowchart.......................................................................379
Figure 15.20 Sample Flowchart of Simultaneous Serial Transmission and Reception...............381
Figure 15.21 IrDA Block Diagram .............................................................................................382
Figure 15.22 IrDA Transmission and Reception.........................................................................383
Figure 15.23 Example of Transmission using DTC in Clocked Synchronous Mode..................387
Figure 15.24 Sample Flowchart for Mode Transition during Transmission ...............................388
Figure 15.25 Pin States during Transmission in Asynchronous Mode (Internal Clock) .............389
Figure 15.26 Pin States during Transmission in Clocked Synchronous Mode
(Internal Clock) ......................................................................................................389
Figure 15.27 Sample Flowchart for Mode Transition during Reception.....................................390
Figure 15.28 Switching from SCK Pins to Port Pins ..................................................................391
Figure 15.29 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins ..........391
Section 16 I²C Bus Interface (IIC) (Optional)
Figure 16.1 Block Diagram of I²C Bus Interface ........................................................................395
Figure 16.2 I²C Bus Interface Connections (Example: This LSI as Master) ...............................396
Figure 16.3 I²C Bus Data Format (I²C Bus Format)....................................................................424
Figure 16.4 I²C Bus Data Format (Formatless) (IIC_0 Only) .....................................................424
Figure 16.5 I²C Bus Data Format (Serial Format).......................................................................425
Figure 16.6 I²C Bus Timing ........................................................................................................425
Figure 16.7 Sample Flowchart for IIC Initialization ...................................................................426
Figure 16.8 Sample Flowchart for Operations in Master Transmit Mode ..................................427
Figure 16.9 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0) .......429
Figure 16.10 Example of Stop Condition Issuance Operation Timing
in Master Transmit Mode (MLS = WAIT = 0) .....................................................429
Figure 16.11 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1) .............430
Figure 16.12 Example of Operation Timing in Master Receive Mode
(MLS = WAIT = 0, HNDS = 1) .............................................................................432
Figure 16.13 Example of Stop Condition Issuance Operation Timing
in Master Receive Mode (MLS = WAIT = 0, HNDS = 1)....................................432
Rev. 2.0, 08/02, page xxvii of xxxviii