HD64F2145 Datasheet, PDF (495/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 16.9 I²C Bus Timing (SCL and SDA Outputs)
Item
Symbol
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition output
setup time
t_SCLO
t
SCLHO
t_SCLLO
t_BUFO
t_STAHO
t_STASO
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave)
t_STOSO
t_SDASO
Data output hold time
t_SDAHO
Note:*
6t
cyc
when
IICX
is
0,
12t
cyc
when
1.
Output Timing
28t_cyc to 256t_cyc
0.5t
SCLO
0.5t_SCLO
0.5t_SCLO – 1t_cyc
0.5t_SCLO – 1t_cyc
1t_SCLO
Unit
ns
ns
ns
ns
ns
ns
0.5t_SCLO + 2t_cyc
ns
1t_SCLLO – 3t_cyc
ns
1t_SCLL – (6t_cyc or 12t_cyc*)
3t_cyc
ns
Notes
See figure
28.29.
4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle t_cyc, as shown in section 28, Electrical
Characteristics. Note that the I²C bus interface AC timing specifications will not be met with a
system clock frequency of less than 5 MHz.
5. The I²C bus interface specification for the SCL rise time t_sr is 1000 ns or less (300 ns for high-
speed mode). In master mode, the I²C bus interface monitors the SCL line and synchronizes
one bit at a time during communication. If t_sr (the time for SCL to go from low to V_IH) exceeds
the time determined by the input clock of the I²C bus interface, the high period of SCL is
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in table 16.10.
Table 16.10 Permissible SCL Rise Time (t_sr) Values
t_cyc
IICX Indication
Time Indication [ns]
I²C Bus
Specification ø =
(Max.)
5 MHz
ø=
8 MHz
ø=
ø=
ø=
10 MHz 16 MHz 20 MHz
0 7.5 t
Standard mode 1000
cyc
High-speed mode 300
1 17.5 t
Standard mode 1000
cyc
High-speed mode 300
1000 937 750 468 375
300 300 300 300 300
100 1000 1000 1000 875
300 300 300 300 300
Rev. 2.0, 08/02, page 455 of 788