HD64F2145 Datasheet, PDF (814/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Item
16.3.8 I²C Bus Extended
Control Register (ICXR)
Section 16 I²C Bus
Interface (IIC) (Optional)
16.4.3 Master Transmit
Operation
Figure 16.9 Example of
Operation Timing in
Master Transmit Mode
(MLS = WAIT = 0)
Page Revisions (See Manual for Details)
422 [Clearing Conditions]
(Error)
ICDRF is set to 1 again.
(Correction)
ICDRE is set to 1 again.
429 (Error)
(Correction)
ICDRS
Address + R/
Note: * Data write
timing in ICDR
Incorrect
operation
Normal
operation
User processing ^{[4] BBSY set to 1}
SCP cleared to 0
(start condition issuance)
ICDRS
Address + R/
Note: Data write
in ICDR
prohibited
User processing ^{[4] BBSY set to 1}
SCP cleared to 0
(start condition issuance)
16.4.4 Master Receive
Operation
430 (Error)
The master device transmits data containing the slave
address and R/: (0: read) in the first frame following the start
condition issuance in master transmit mode, selects the slave
device, and then switches the mode for receive operation.
(Correction)
The master device transmits data containing the slave
address and R/: (1: read) in the first frame following the start
condition issuance in master transmit mode, selects the slave
device, and then switches the mode for receive operation.
Rev. 2.0, 08/02, page 774 of 788