HD64F2145 Datasheet, PDF (505/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Section 17 Keyboard Buffer Controller
This LSI has three on-chip keyboard buffer controller channels. The keyboard buffer controller is
provided with functions conforming to the PS/2 interface specifications.
Data transfer using the keyboard buffer controller employs a data line (KD) and a clock line
(KCLK), providing economical use of connectors, board surface area, etc. Figure 17.1 shows a
block diagram of the keyboard buffer controller.
17.1 Features
• Conforms to PS/2 interface specifications
• Direct bus drive (via the KCLK and KD pins)
• Interrupt sources: on completion of data reception and on detection of clock edge
• Error detection: parity error and stop bit monitoring
KBBR
Internal
data bus
KD
(PS2AD,
PS2BD,
PS2CD)
KCLK
(PS2AC,
PS2BC,
PS2CC)
KDI
Control _KCLKI
logic
Parity
KDO
KCLKO
KBCRH
KBCRL
Register counter value
KBI interrupt
Legend
KD:
KBC data I/O pin
KCLK: KBC clock I/O pin
KBBR: Keyboard data buffer register
KBCRH: Keyboard control register H
KBCRL: Keyboard control register L
Figure 17.1 Block Diagram of Keyboard Buffer Controller
IFKEY10A_000020020700
Rev. 2.0, 08/02, page 465 of 788