HD64F2145 Datasheet, PDF (131/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

• ISCRL
Bit Bit Name Initial Value R/W
7
IRQ3SCB 0
R/W
6
IRQ3SCA 0
R/W
5
IRQ2SCB 0
R/W
4
IRQ2SCA 0
R/W
3
IRQ1SCB 0
R/W
2
IRQ1SCA 0
R/W
1
IRQ0SCB 0
R/W
0
IRQ0SCA 0
R/W
Description
IRQn Sense Control B
IRQn Sense Control A
00: Interrupt request generated at low level of
,54Q input
01: Interrupt request generated at falling edge
of ,54Q input
10: Interrupt request generated at rising edge of
,54Q input
11: Interrupt request generated at both falling
and rising edges of ,54Q input
(n = 3 to 0)
5.3.5 IRQ Enable Register (IER)
IER controls the enabling and disabling of interrupt requests IRQ7 to IRQ0.
Bit Bit Name Initial Value R/W
7
IRQ7E
0
R/W
6
IRQ6E
0
R/W
5
IRQ5E
0
R/W
4
IRQ4E
0
R/W
3
IRQ3E
0
R/W
2
IRQ2E
0
R/W
1
IRQ1E
0
R/W
0
IRQ0E
0
R/W
Description
IRQn Enable (n = 7 to 0)
The IRQn interrupt request is enabled when this
bit is 1.
Rev. 2.0, 08/02, page 91 of 788