HD64F2145 Datasheet, PDF (564/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

R/W
Bit Bit Name Initial Value Slave Host Description
4 SWMF 0
R/(W)* R Slave Write Mode Flag
Set to 1 when the slave processor (this LSI) writes to
TWR0. In the event of simultaneous writes by the
master and the slave, the master write has priority.
SWMF is cleared to 0 when the host reads TWR15
0: [Clearing condition]
When the host processor reads TWR15 using I/O
read cycle, or the slave processor writes 0 to the
SWMF bit
1: [Setting condition]
When the slave processor writes to TWR0 while
MWMF = 0
3 C/D3
0
R
R Command/Data
When the host processor writes to an IDR register,
bit 2 of the I/O address is written into this bit to
indicate whether IDR contains data or a command.
0: Contents of data register (IDR) are data
1: Contents of data register (IDR) are a command
2 DBU32 0
R/W R Defined by User
The user can use this bit as necessary.
1 IBF3A 0
R
R Input Buffer Full
Set to 1 when the host processor writes to IDR. This
bit is an internal interrupt source to the slave
processor (this LSI). IBF is cleared to 0 when the
slave processor reads IDR.
The IBF1 flag setting and clearing conditions are
different when the fast A20 gate is used. For details
see table 19.3.
0: [Clearing condition]
When the slave processor reads IDR
1: [Setting condition]
When the host processor writes to IDR using I/O
write cycle
Rev. 2.0, 08/02, page 524 of 788