HD64F2145 Datasheet, PDF (801/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Item
Page Revisions (See Manual for Details)
5.3.7 Keyboard Matrix 92
Interrupt Mask Registers
(KMIMRA, KMIMR)
93
Wake-Up Event Interrupt
Mask Register
(WUEMRB)
(Error) The KMIMR and WUEMR registers
(Correction) The KMIMRA, KMIMR, and WUEMRB registers
Added.
• WUEMRB*
Note:* Not supported by the H8S/2148B.
5.4 Interrupt Sources
95
5.4.1 External Interrupts
Table 5.3 Interrupt
98
Sources, Vector
Addresses, and Interrupt
Priorities
Description added to IRQ7 to IRQ0 Interrupts.
• Interrupt control levels can be specified by the ICR
settings.
(Error)
Origin of
Interrupt
Source
Name
Vector
Number
Vector Address
Normal
Mode
Advanced
Mode

Reserved for system use
100
H'00C8
H'000190
101
H'00CA
H'000194
102
H'00CC
H'000198
103
H'00CE
H'00019C
LPC*
ERRI (Transfer error)
112
IBF1 (IDR1 reception completion) 113
IBF2 (IDR2 reception completion) 114
IBF3 (IDR3 reception completion)
H'00D0
H'00DA
H'00DC
H'00DE
H'0001B0
H'0001B4
H'0001B8
H'0001BC
(Correction)
Origin of
Interrupt
Source
Name
Vector
Number
Vector Address
Normal
Mode
Advanced
Mode

LPC*
Reserved for system use
100
to
107
ERRI (Transfer error)
108
IBF1 (IDR1 reception completion) 109
IBF2 (IDR2 reception completion) 110
IBF3 (IDR3 reception completion) 111
H'00C8
to
H'00D6
H'00D8
H'00DA
H'00DC
H'00DE
H'000190
to
H'0001AC
H'0001B0
H'0001B4
H'0001B8
H'0001BC
5.6.1 Interrupt Control 99
Mode 0
5.6.4 Interrupt Response 105
Times
Table 5.6 Number of
States in Interrupt
Handling Routine
Execution Status
In interrupt control mode 0, interrupt requests other than NMI
and address breaks
Corrected.
Object of Access
External Device
8-Bit Bus
16-Bit Bus
2-State Access 3-State Access 2-State Access 3-State Access
4
6 + 2m
2
3+m
Rev. 2.0, 08/02, page 761 of 788