HD64F2145 Datasheet, PDF (489/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

When FS = 1 and FSX = 1 (clocked synchronous serial format)
SCL
7
8
1
2
3
4
SDA
7
8
1
2
3
4
IRIC
User processing
Clear IRIC
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
SCL
7
8
1
SDA
7
8
1
IRIC
User processing
Clear IRIC
Write to ICDR (transmit)
or read from ICDR (receive)
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.
Clear IRIC
Figure 16.28 IRIC Setting Timing and SCL Control (3)
16.4.8 Automatic Switching from Formatless Mode to I²C Bus Format
Setting the SW bit to 1 in DDCSWR enables formatless mode to be selected as the IIC_0
operating mode. Switching from formatless mode to the I²C bus format (slave mode) is performed
automatically when a falling edge is detected on the SCL pin.
The following four preconditions are necessary for this operation:
• A common data pin (SDA) for formatless and I²C bus format operation
• Separate clock pins for formatless operation (VSYNCI) and I²C bus format operation (SCL)
• A fixed 1 level for the SCL pin during formatless operation (the SCL pin does not output a low
level)
• Settings of bits other than TRS in ICCR that allow I²C bus format operation
Rev. 2.0, 08/02, page 449 of 788