HD64F2145 Datasheet, PDF (188/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

In the case of transfer with the CHNE bit set to 1, an interrupt request to the CPU is not generated
at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
Source
DTC vector
address
Register information
start address
Register information
CHNE = 1
Register information
CHNE = 0
Destination
Source
Destination
Figure 7.8 Chain Transfer Operation
7.5.5 Interrupts
An interrupt request is issued to the CPU when the DTC has completed the specified number of
data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt
activation, the interrupt set as the activation source is generated. These interrupts to the CPU are
subject to CPU mask level and priority level control by the interrupt controller.
In the case of software activation, a software-activated data transfer end interrupt (SWDTEND) is
generated.
When the DISEL bit is 1 and one data transfer has been completed, or the specified number of
transfers have been completed, after data transfer ends, the SWDTE bit is held at 1 and an
SWDTEND interrupt is generated. The interrupt handling routine will then clear the SWDTE bit
to 0.
When the DTC is activated by software, an SWDTEND interrupt is not generated during a data
transfer wait or during data transfer even if the SWDTE bit is set to 1.
Rev. 2.0, 08/02, page 148 of 788