HD64F2145 Datasheet, PDF (649/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Section 25 Clock Pulse Generator
This LSI incorporates a clock pulse generator, which generates the system clock (ø), bus master
clock, and internal clock.
The clock pulse generator consists of an oscillator, duty correction circuit, clock select circuit,
medium-speed clock divider, bus master clock select circuit, subclock input circuit, and waveform
forming circuit. Figure 25.1 shows a block diagram of the clock pulse generator.
EXTAL
XTAL
Oscillator
Duty
correction
circuit
Clock select
circuit
øSUB
Medium-
speed clock
divider
ø/2
to f/32
ø
Bus master
clock select
circuit
EXCL
Subclock
input circuit
Waveform
forming
circuit
WDT_1
count clock
System clock
to ø pin
Internal clock
to peripheral
modules
Bus master clock
to CPU and DTC
Figure 25.1 Block Diagram of Clock Pulse Generator
The bus master clock is selected as either high-speed mode or medium-speed mode by software
according to the settings of the SCK2 to SCK0 bits in the standby control register. For details on
the standby control register, refer to section 26.1.1, Standby Control Register (SBYCR).
The subclock input is controlled by software according to the EXCLE bit setting in the low power
control register. For details on the low power control register, refer to section 26.1.2, Low Power
Control Register (LPWRCR).
Rev. 2.0, 08/02, page 609 of 788