HD64F2145 Datasheet, PDF (366/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

WOVI0
(Interrupt request signal)
Internal NMI
(Interrupt request signal*²)
signal*¹
Internal reset signal*¹
Interrupt
control
Reset
control
Overflow
Clock
Clock
selection
ø/2
ø/64
ø/128
ø/512
ø/2048
ø/8192
ø/32768
ø/131072
Internal clock
TCNT_0
TCSR_0
Module bus
WDT_0
Bus
interface
WOVI1
(Interrupt request signal)
Internal NMI
(Interrupt request signal*²)
signal*¹
Internal reset signal*¹
Interrupt
control
Reset
control
Overflow
Clock
Clock
selection
ø/2
øSUB/2
ø/64
øSUB/4
ø/128
øSUB/8
ø/512
øSUB/16
ø/2048 _øSUB/32
ø/8192 _øSUB/64
ø/32768 _øSUB/128
ø/131072 _øSUB/256
Internal clock
TCNT_1
TCSR_1
Module bus
Bus
interface
Legend
TCSR_0
TCNT_0
TCSR_1
TCNT_1
WDT_1
: Timer control/status register_0
: Timer counter_0
: Timer control/status register_1
: Timer counter_1
Notes: 1. The
signal outputs the low level signal when the internal reset signal is
generated due to a TCNT overflow of either WDT_0 or WDT_1. The internal reset signal
first resets the WDT in which the overflow has occurred first.
2. The internal NMI interrupt signal can be independently output from either WDT_0 or WDT_1.
The interrupt controller does not distinguish the NMI interrupt request from WDT_0 from
that from WDT_1.
Figure 14.1 Block Diagram of WDT
Rev. 2.0, 08/02, page 326 of 788