HD64F2145 Datasheet, PDF (480/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Start condition generation
[7] SCL is fixed low until ICDR is read
SCL
(Pin waveform)
1
2
3
4
5
6
7
8
9
1
2
SCL
(master output)
1
2
3
4
5
6
7
8
9
1
2
SCL
(slave output)
SDA
(master output)
SDA
(slave output)
IRIC
ICDRF
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Slave address
R/
[6]
A
Interrupt
request
occurrence
Bit 7 Bit 6
Data 1
ICDRS
Address+R/
ICDRR
Undefined value
Address+R/
User processing _{[2] ICDR read}
[8] IRIC clear
[10] ICDR read (dummy read)
Figure 16.19 Example of Slave Receive Mode Operation Timing (1)
(MLS = 0, HNDS= 1)
SCL
(master output)
[7] SCL is fixed low until ICDR is read
8
9
12
3
4
Stop condition generation
[7] SCL is fixed low until ICDR is read
5
6
7
8
9
SCL
(slave output)
SDA
(master output) ^{Bit 0}
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data (n-1)
[6]
Data (n)
[6]
[11]
SDA
(slave output)
A
A
IRIC
ICDRF
ICDRS
Data (n-1)
ICDRR Data (n-2)
Data (n-1)
Data (n)
Data (n)
User processing
[8] IRIC clear [5] ICDR read (Data (n-1))
[9] Set ACKB=1
[8] IRIC clear
[10] ICDR read
(Data (n))
[12] IRIC clear
Figure 16.20 Example of Slave Receive Mode Operation Timing (2)
(MLS = 0, HNDS= 1)
Rev. 2.0, 08/02, page 440 of 788