HD64F2145 Datasheet, PDF (31/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Figure 17.13 Example of KCLK Input Fall Interrupt Operation.................................................480
Figure 17.14 KBIOE Setting and KCLK Falling Edge Detection Timing..................................481
Section 18 Host Interface X-Bus Interface (XBS)
Figure 18.1 Block Diagram of XBS............................................................................................484
Figure 18.2 GA20 Output ...........................................................................................................496
Figure 18.3 HIRQ Output Flowchart (Example of Channels 1 and 2)........................................500
Section 19 Host Interface LPC Interface (LPC)
Figure 19.1 Block Diagram of LPC ............................................................................................504
Figure 19.2 Typical /)5$0( Timing .......................................................................................538
Figure 19.3 Abort Mechanism .................................................................................................. ..538
Figure 19.4 GA20 Output ...........................................................................................................540
Figure 19.5 Power-Down State Termination Timing..................................................................545
Figure 19.6 SERIRQ Timing ......................................................................................................546
Figure 19.7 Clock Start Request Timing.....................................................................................548
Figure 19.8 HIRQ Flowchart (Example of Channel 1) ...............................................................551
Section 20 D/A Converter
Figure 20.1 Block Diagram of D/A Converter............................................................................553
Figure 20.2 D/A Converter Operation Example .........................................................................556
Section 21 A/D Converter
Figure 21.1 Block Diagram of A/D Converter............................................................................560
Figure 21.2 Example of A/D Converter Operation
(Scan Mode, Channels AN0 to AN2 Selected) ........................................................567
Figure 21.3 A/D Conversion Timing ..........................................................................................568
Figure 21.4 External Trigger Input Timing.................................................................................569
Figure 21.5 A/D Conversion Accuracy Definitions ....................................................................571
Figure 21.6 A/D Conversion Accuracy Definitions ....................................................................571
Figure 21.7 Example of Analog Input Circuit.............................................................................572
Figure 21.8 Example of Analog Input Protection Circuit ...........................................................574
Figure 21.9 Equivalent Circuit of Analog Input Pin ...................................................................574
Section 23 ROM
Figure 23.1 Block Diagram of Flash Memory ............................................................................578
Figure 23.2 Flash Memory State Transitions ..............................................................................579
Figure 23.3 Boot Mode ...............................................................................................................580
Figure 23.4 User Program Mode (Example) ...............................................................................581
Figure 23.5 64-Kbyte Flash Memory Block Configuration ........................................................582
Figure 23.6 128-Kbyte Flash Memory Block Configuration ......................................................583
Figure 23.7 256-Kbyte Flash Memory Block Configuration ......................................................584
Figure 23.8 On-Chip RAM Area in Boot Mode .........................................................................595
Figure 23.9 ID Code Area...........................................................................................................596
Figure 23.10 Programming/Erasing Flowchart Example in User Program Mode ......................597
Figure 23.11 Program/Program-Verify Flowchart......................................................................599
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