HD64F2145 Datasheet, PDF (411/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

15.5.2 Multiprocessor Serial Data Reception
Figure 15.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data
with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is
generated at this time. All other SCI operations are the same as in asynchronous mode. Figure
15.12 shows an example of SCI operation for multiprocessor format reception.
Start
1 bit
Data (ID1)
Stop Start
MPB bit bit
Data (Data 1)
Stop
MPB bit
1
0 D0 D1
D7 1 1 0 D0 D1
D7 0
1 Idle state
(mark state)
MPIE
RDRF
RDR
value
ID1
MPIE = 0
RXI interrupt
request
(multiprocessor
interrupt)
generated
RDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
handling routine
If not this station’s ID, RXI interrupt request is
MPIE bit is set to 1
not generated, and RDR
again
retains its state
(a) Data does not match station’s ID
Start
1 bit
Data (ID2)
Stop Start
MPB bit bit
Data (Data 2)
Stop
MPB bit
1
0 D0 D1
D7 1 1 0 D0 D1
D7 0
1 Idle state
(mark state)
MPIE
RDRF
RDR
value
ID1
MPIE = 0
ID2
Data 2
RXI interrupt
request
(multiprocessor
interrupt)
generated
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
handling routine
Matches this station’s ID,
so reception continues, and
data is received in RXI
interrupt service routine
MPIE bit set to 1
again
(b) Data matches station’s ID
Figure 15.12 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor
Bit, One Stop Bit)
Rev. 2.0, 08/02, page 371 of 788