HD64F2145 Datasheet, PDF (499/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Figure 16.31 shows the timing of start condition issuance for retransmission, and the timing for
subsequently writing data to ICDR, together with the corresponding flowchart. Write the
transmit data to ICDR after the start condition for retransmission is issued and then the start
condition is actually generated.
IRIC = 1?
No
[1]
Yes
Clear IRIC in ICSR
Start condition
issuance?
Yes
Read SCL pin
SCL = Low?
Yes
Set BBSY = 1,
SCP = 0 (ICSR)
No
Other processing
No
[2]
[3]
IRIC = 1?
[4]
No
Yes
Write transmit data to ICDR
[5]
[1] Wait for end of 1-byte transfer
[2] Determine whether SCL is low
[3] Issue start condition instruction for retransmission
[4] Determine whether start condition is generated or not
[5] Set transmit data (slave address + R/ )
Note:* Program so that processing from [3] to [5]
is executed continuously.
SCL
SDA
9
ACK
Start condition generation
(retransmission)
bit7
IRIC
[1] IRIC determination
[5] ICDR write (transmit data)
[4] IRIC determination
[3] (Retransmission) Start condition instruction issuance
[2] Determination of SCL = Low
Figure 16.31 Flowchart for Start Condition Issuance Instruction for Retransmission and
Timing
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in
ICXR.
Rev. 2.0, 08/02, page 459 of 788